This invention relates to random access memory circuits, particularly such circuits adapted for high speed operation and low power dissipation.
In recent years, increasing interest has developed in the use of GaAs materials for high speed digital integrated circuits. Rapid progress in developing this technology has been stimulated by the availability of existing equipment and sophisticated processing techniques which were developed for silicon based semiconductor technologies.
The switch to GaAs devices has been prompted by the need for a semiconductor with higher performance than silicon as high speed semiconductor technologies approach the physical limits of their performance, which is determined by the minimum dimensions which are attainable.
Any digital integrated circuit technology, however, must be accompanied by compatible memory circuits to be useful in practical applications. Space based satellites, for example, are widely used in communications systems, and it is anticipated that in the future numerous defense, surveillance, and intelligence missions will require space-based radar, communications, and electro-optical systems. This equipment will require high speed signal processing to be accomplished on board the space vehicle prior to data transmission. This processing capability will, in turn, require large quantities of random access memory (RAM).
One of the most critical design constraints imposed on such memory circuits by space applications is the need for a low power dissipation, typically approximately 1 microwatt (uW) per bit of memory. In addition, this power limitation must be satisfied while maintaining a sufficiently fast access time, typically less than 10 nanoseconds (ns). Another important design constraint is radiation hardening, with radiation resistance required against total doses in excess of one million rads. The radiation resistance of GaAs integrated circuits, combined with their high speed and low power capabilities, makes this technology ideal for a RAM which is to be used in such applications.
The rate of access of RAM in a signal processing application is very low because of the large memory size. Thus it is the static power used by each bit cell in the RAM which will predominate in the overall power consumption of the memory, provided the chip peripherals, such as address decoders, bit sense amplifiers, etc., are powered down when a particular chip is not accessed for a read or write. The static power Pd consumed by a RAM cell is given by: EQU Pd=VddIdd
where Vdd is the supply voltage and Idd is the static supply current. The design challenge, therefore, is to reduce Idd for the RAM cells, consistent with proper cell functioning and allowing for statistical variations in the parameters.
In the case of a GaAs static RAM, the key design problem is not so much the attainment of a fast access time, but obtaining such high speed operation while simultaneously holding the power dissipation levels low. If, for example, a 4096 bit (4K) memory is arranged in a 64.times.64 bit array, the total bit sense line capacitance on one of the 64 cell columns will be approximately 425 pF, including overcrossings, stray line capacitances, and the diode input capacitance at each cell. Using the smallest practical GaAs field effect transistor (FET) as the active load in the cell, with a width of 1 .mu.m and a threshold voltage of Vp=-0.7 V, the current will be 20 uA. This current would discharge the bit line by 0.75 V in 15 ns. For an access time Tacc of 10 ns, the maximum discharge time will be approximately 4 ns and such a memory cell must sink a current of 0.82 mA to achieve this. With 4K cells operating at 0.82 mA quiescent current levels and Vdd=3 V, the total chip power dissipation would be an unacceptably high 10 W. Consequently, a need has arisen in the random access memory art for a RAM circuit which will achieve a fast access time without affecting the power dissipation of unaddressed cells.